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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr st16c1550/51 2.97v to 5.5v uart with 16-byte fifo august 2005 rev. 4.2.1 general description the st16c1550 and st16c1551 uarts (here on denoted as the st16c155x) are improved versions of the ssi 73m1550 and ssi 73m2550 uart with higher operating speed and lower access time. the st16c155x provides enhanced uart functions with 16 byte fifos, a modem control interface, independent programmable baud rate generators with clock rates up to 1.5 mbps. onboard status registers provide the user with error indications and operational status. system interrupt and modem control features may be tailored by external software to meet specific user requirements. an internal loopback capability allows o nboard diagnost ics. the baud rate generator can be configured for either crystal or external clock input with the exception of the 28 pin st16c1551 package (where an external clock must be provided). each package type, with the exception of the 28 pin st16c155x, provides a buffered reset output that can be controlled through user software. dma monitor signals txrdy/rxrdy are not available at the st16c155x i/o pins but these signals are accessible through isr register bits 4-5. except as listed above, all package versions have the same features. the st16c155x is not compatible with th e industry standard 16550 and will not work with the standard serial port driver in ms windows (see pages 16-17 for details) . for an ms windows compatible uart, see the st16c550. features ? pin and functionally compatible to ssi 73m1550/ 2550 ? 16 byte transmit fifo ? 16 byte receive fifo with error flags ? 4 selectable receive fifo interrupt tr igger levels ? modem control signals (cts#, rts#, dsr#, dtr#, ri#, cd#) ? programmable character lengths (5, 6, 7, 8) with even, odd or no parity ? crystal or external clock input (except 28 pin st16c1551, external clock only) ? 1.5 mbps transmit/receive operation (24 mhz) with programmable clock control ? power down mode (50 ua at 3.3 v, 200 ua at 5 v) ? software controllable reset output ? 2.97 to 5.5 volt operation applications ? battery operated electronics ? internet appliances ? handheld terminal ? personal digital assistants ? cellular phones dataport f igure 1. b lock d iagram xtal1/clk xtal2 crystal osc/buffer dtr#, rts# dsr#, cts#, cd#, ri# data bus interface 16 byte tx fifo baud rate generator transmitter uart configuration regs ior# 16 byte rx fifo receiver modem control signals tx rx int a2:a0 d7:d0 cs# iow# reset rst
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 2 f igure 2. st16c1550 p inouts 28-plcc packages 48-tqfp package 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 n.c. n.c. d4 d5 d6 d7 rx tx cs# n.c. n.c. n.c. n.c. n.c. cts# reset dtr# rts# a0 n.c. a1 a2 n.c. n.c. n.c. d3 d2 d1 n.c. d0 n.c. vcc cd# dsr# n.c. n.c. n.c. n.c. xtal1 xtal2 iow# n.c. gnd ior# ri# rst int n.c. st16c1550cq48 4 3 2 1 28 27 26 5 6 7 8 9 10 11 25 24 23 22 21 20 19 12 13 14 15 16 17 18 d4 d5 d6 d7 rx tx cs# cts# reset dtr# rts# a0 a1 a2 d3 d2 d1 d0 vcc cd# dsr# xtal1 xtal2 iow# gnd ior# ri# int st16c1550cj28 n ote : pinouts not to scale . actual size of tqfp package is smaller than plcc package .
xr st16c1550/51 rev. 4.2.1 2.97v to 5.5v uart with 16-byte fifo 3 f igure 3. st16c1551 p inouts 28-plcc packages 48-tqfp package 4 3 2 1 28 27 26 5 6 7 8 9 10 11 25 24 23 22 21 20 19 12 13 14 15 16 17 18 d4 d5 d6 d7 rx tx cs# cts# reset dtr# rts# a0 a1 a2 d3 d2 d1 d0 vcc cd# dsr# clk iow# gnd ior# ri# rst int st16c1551cj28 n ote : pinouts not to scale . actual size of tqfp package is smaller than plcc package . 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 n.c. n.c. d4 d5 d6 d7 rx tx cs# n.c. n.c. n.c. n.c. n.c. cts# reset dtr# rts# a0 n.c. a1 a2 n.c. n.c. n.c. d3 d2 d1 n.c. d0 n.c. vcc cd# dsr# n.c. n.c. n.c. n.c. xtal1 xtal2 iow# n.c. gnd ior# ri# rst int n.c. st16c1551cq48
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 4 ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus st16c1550cj28 28-lead plcc 0c to +70c active st16c1550cq48 48-lead tqfp 0c to +70c active st16c1551cj28 28-lead plcc 0c to +70c active st16c1551cq48 48-lead tqfp 0c to +70c active st16c1550ij28 28-lead plcc -40c to +85c active st16c1550iq48 48-lead tqfp -40c to +85c active st16c1551ij28 28-lead plcc -40c to +85c active st16c1551iq48 48-lead tqfp -40c to +85c active
xr st16c1550/51 rev. 4.2.1 2.97v to 5.5v uart with 16-byte fifo 5 pin descriptions n ame 28-p in plcc (1550) 28-p in plcc (1551) 48-p in tqfp t ype d escription data bus interface a0 a1 a2 21 20 19 21 20 19 30 28 27 i address data lines [2:0]. a2:a0 selects internal uart?s configuration regis - ters. d0 d1 d2 d3 d4 d5 d6 d7 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 43 45 46 47 3 4 5 6 i/o data bus lines [7:0] (bidirectional). ior# 16 15 20 i input/output read (active low). the fal ling edge instigates an internal read cycle and retrieves the data byte from an internal regist er pointed by the address lines [a2:a0], places it on the data bus to allow the host processor to read it on the leading edge. iow# 14 13 17 i input/output write (active low). the fall ing edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines [a2:a0]. cs# 11 11 9 i chip select input (active low). a logic 0 on this pin selects the st16c155x device. int 18 18 23 o interrupt output (three-state, active hi gh). int output defaults to three-state mode and becomes active high when mcr bit-3 is set to a logic 1. int output becomes a logic high level when interrupts are enabled in the interrupt enable register (ier), and whenever the transmitter, receiver, line and/or modem sta - tus register has an active condition. modem or serial i/o interface tx 10 10 8 o transmit data. this output is associated with individual serial transmit chan - nel data from the 155x. the tx signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. during the local loopback mode, the tx output pin is disabled and tx data is internally connected to the uart rx input. rx 9 9 7 i receive data. this input is associated with individual serial channel data to the 155x. normal received data input idle s at logic 1 condition. this input must be connected to its idle logic state, logic 1, else the receiver may report ?receive break? and/or ?error? condition(s). rts# 22 22 31 o request to send or general purpose output (active low). if this pin is not needed for modem communication, then it ca n be used as a general i/o. if it is not used, leave it unconnected. cts# 25 25 34 i clear to send or general purpose input (a ctive low). if this pin is not needed for modem communication, then it can be used as a general i/o. if it is not used, connect it to vcc.
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 6 pin type: i=input, o=output, i/o= input/output, od=output open drain. dtr# 23 23 32 o data terminal ready or general purpose output (active low). if this pin is not needed for modem communication, then it ca n be used as a general i/o. if it is not used, leave it unconnected. dsr# 26 26 39 i data set ready input or general purpose input (active low). if this pin is not needed for modem communication, then it ca n be used as a general i/o. if it is not used, connect it to vcc. cd# 27 27 40 i carrier detect input or general purpose input (active low). if this pin is not needed for modem communication, then it ca n be used as a general i/o. if it is not used, connect it to vcc. ri# 17 16 21 i ring indicator input or general purpose input (active low). if this pin is not needed for modem communication, then it ca n be used as a general i/o. if it is not used, connect it to vcc. ancillary signals clk - 12 - i external clock input. this function is associated with 28 pin pdip and 28 pin plcc packages only. an external clock must be connected to this pin to clock the baud rate generator and internal circuitry. xtal1 12 - 15 i crystal or external clock input. see figure 4 for typical oscillator connec - tions. xtal2 13 - 16 o crystal or buffered clock output. see figure 4 for typical oscillator connec - tions. reset 24 24 33 i reset input (active high). when it is asserted, the uart configuration regis - ters are reset to default values, see table 8 . rst - 17 22 o reset output (active high). this outpu t is only available on the st16c1551. when ier bit-5 is a logic 0, rst will follow the logical state of the reset pin. when ier bit-5 is a logic 1, the user may send software (soft) resets via mcr bit-2. soft resets from mcr bit-2 are ?ored? with the state of the reset pin. vcc 28 28 41 pwr power supply input. gnd 15 14 19 pwr power supply common ground. n.c. - - 1, 2, 10-14, 18, 24-26, 29, 35-38, 42, 44, 48 - not connected. n ame 28-p in plcc (1550) 28-p in plcc (1551) 48-p in tqfp t ype d escription
xr st16c1550/51 rev. 4.2.1 2.97v to 5.5v uart with 16-byte fifo 7 1.0 product description the st16c155x provides serial asynchronous receive da ta synchronization, paralle l-to-serial and serial-to- parallel data conversions for both the transmitter and receiver sections. these functions are necessary for converting the serial data stream into parallel data that is required in digital data systems. synchronization for the serial data stream is accomplished by adding star t and stops bits to the transmit data to form a data character (character orientated protocol). data integr ity is ensured by attaching a parity bit to the data character. the parity bit is checked by th e receiver for any transmission bit errors. e nhanced f eatures the st16c155x is an upward solution that provides 16 bytes of transmit and receiv e fifo memory, instead of none in the 16c145x. the 155x is designed to work with high speed modems and shared network environments, that require fast data processing time. increased performance is realized in the 155x by the larger transmit and receive fifos. th is allows the external processor to handle more networking tasks within a given time. for example, the st16c550 with a 16 by te fifo, unloads 16 bytes of receive data in 93 microseconds (this example uses a character length of 11 bits, including start/stop bits at 115.2kbps). this means the external cpu will have to service the rece ive fifo less than every 10 0 microseconds. however with the 16 byte fifo in th e 155x, the data buffer will not require unloading/loading fo r 1.53 ms. this increases the service interval giving the external cpu additional time for other applications and reducing the overall uart interrupt servicing time. in addition, the 4 select able levels of fifo trigger interrupt are provided for maximum data throughput performance especially when operating in a multi-channel environment. the fifo memory greatly reduces the bandwidth requirement of the external controlling cp u, increases performance, and reduces power consumption. d ata r ate the 155x is capable of operation up to 1.5 mbps wi th a 24 mhz crystal or external clock input with a 16x sampling clock (at vcc = 5.0v). with a crystal of 14.7456 mhz and through a software option, the user can select data rates up to 921.6 kbps. the rich feature set of the 155x is available through inte rnal registers. selectable receive fifo trigger levels, selectable baud rates, and modem interface controls are all standard features. following a power on reset or an external reset, the 155x is soft ware compatible with the st16c145x.
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 8 2.0 functional descriptions 2.1 internal registers the 155x has a set of enhanced registers for controlling, monitoring and data loading and unloading. these registers function as data holding r egisters (thr/rhr), interrupt status and control registers (isr/ier), a fifo control register (fcr), receive line status and control registers (lsr/lcr), modem status and control registers (msr/mcr), programmable data rate (clock) divisor regi sters (dll/dlm), and a user accessible scractchpad register (spr). all the register functions are discussed in full detail later in ?section 3.0, uart internal registers? on page 14 . 2.2 dma mode the dma mode (a legacy term) in this document does not mean ?direct memory access? but refers to data block transfer operation. the dma mode affects the stat e of the rxrdy and txrdy bits (isr bits 5 and 4 respectively). the tran smit and receive fifo trigger levels provide additional flexibility to the user for block mode operation. the lsr bits 5-6 provide an indicati on when the transmitter is empty or has an empty location(s) for more data. the user can optionally operate the transmit and receive fifo in the dma mode (fcr bit-3=1). when the transmit and receive fifo ar e enabled and the dma mode is disabled (fcr bit-3 = 0), the 155x activates the txrdy & rxrdy output pin for each data transmit or receive operation. when dma mode is enabled (fcr bit-3 = 1), the user takes advantage of block mode operation by loading or unloading the fifo in a block sequence determined by the programmed trigger level. in this mode, the 155x sets the txrdy bit when the transmit fifo becomes full, and sets the rxrdy pin when the receive fifo becomes empty. the following table shows their behavior. 2.3 crystal oscillator or external clock the 155x includes an on-chip oscilla tor (xtal1 and xtal2). the crystal os cillator provides the system clock to the baud rate generators (brg) in the uart. xtal1 is the input to the oscillator or ex ternal clock buffer input with xtal2 pin being the output. for programming details, see ?section 2.4, programmable baud rate generator? on page 9 . the on-chip oscillator is designed to use an industry standard micropro cessor crystal (p arallel resonant, fundamental frequency with 10-22 pf capacitance load, esr of 20-120 ohms and 100ppm frequency tolerance) connected externally between the xtal1 and xtal2 pins (see figure 4 ). alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates. typical oscillator conn ections are shown in figure 4 . for further reading on os cillator circuit please see application note dan108 on exar?s web site. t able 1: txrdy and rxrdy b its in fifo and dma m ode p ins fcr bit -0=0 (fifo d isabled ) fcr b it -0=1 (fifo e nabled ) fcr bit-3 = 0 (dma mode disabled) fcr bit-3 = 1 (dma mode enabled) rxrdy 1 = 1 byte 0 = no data 1 = at least 1 byte in fifo 0 = fifo empty 1 = fifo reaches the trigger level, or timeout occurs 0 = fifo empty txrdy 1 = thr empty 0 = byte in thr 1 = fifo empty 0 = at least 1 byte in fifo 1 = fifo has at least 1 empty location 0 = fifo is full
xr st16c1550/51 rev. 4.2.1 2.97v to 5.5v uart with 16-byte fifo 9 2.4 programmable baud rate generator the uart has its own baud rate gene rator (brg) with a prescaler. the pres caler is controlled by a software bit in the mcr register. the mcr register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. the clock output of the prescaler goes to the brg. the brg further divides this clock by a programmable divisor between 1 and (2 16 -1) to obtain a 16x sampling clock of the serial data rate. the sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. the brg divisor (dll and dlm registers) defaults to a random value upon power up or a reset. therefore, the brg must be programmed during initialization to the operating data rate. programming the baud rate generator registers dlm and dll provides the capability of selecting the operating data rate. table 2 shows the standard data rates available with a 14.7456 mhz crystal or external clock at 16x clock rate. when using a non-standard data rate crystal or external clock, the divisor value can be calculated for dll/dlm with the following equation. f igure 4. t ypical oscillator connections divisor (decimal) = (xtal1 clock frequency / prescaler) / (serial data rate x 16) c1 22-47pf c2 22-47pf y1 1.8432 mhz to 24 mhz r1 0-120 (optional) r2 500k - 1m xtal1 xtal2
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 10 2.5 transmitter the transmitter section comprises of an 8-bit transmit shift register (tsr) and 16 bytes of fifo which includes a byte-wide transmit holding register (thr). tsr shifts out every data bit with the 16x internal clock. a bit time is 16 clock periods. the transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop -bit(s). the status of the fi fo and tsr are reported in the line status register (lsr bit-5 and bit-6). 2.5.1 transmit holding regi ster (thr) - write only the transmit holding register is an 8-bit register pr oviding a data interface to the host processor. the host writes transmit data byte to the thr to be converted in to a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-si gnificant-bit (bit-0) becomes first data bit to go out. the thr is the input register to the transmit fifo of 16 bytes when fifo operation is enabl ed by fcr bit-0. every time a write operation is made to the thr, the fifo data pointer is automatically bumped to the next sequential data location. t able 2: t ypical data rates with a 14.7456 mh z crystal or external clock o utput data rate mcr bit-7=1 o utput data rate mcr bit-7=0 d ivisor for 16x clock (decimal) d ivisor for 16x clock (hex) dlm p rogram v alue (hex) dll p rogram v alue (hex) d ata r ate e rror (%) 100 400 2304 900 09 00 0 600 2400 384 180 01 80 0 1200 4800 192 c0 00 c0 0 2400 9600 96 60 00 60 0 4800 19.2k 48 30 00 30 0 9600 38.4k 24 18 00 18 0 19.2k 76.8k 12 0c 00 0c 0 38.4k 153.6k 6 06 00 06 0 57.6k 230.4k 4 04 00 04 0 115.2k 460.8k 2 02 00 02 0 230.4k 921.6k 1 01 00 01 0
xr st16c1550/51 rev. 4.2.1 2.97v to 5.5v uart with 16-byte fifo 11 2.5.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a transmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr beco mes completely empty. 2.5.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 16 bytes of transmit data. t he thr empty flag (lsr bit-5) is set whenever the fifo is empty. the thr empty flag can ge nerate a transmit empty interrupt (isr bit-1) when the amount of data in the fifo falls below its programmed trig ger level. the transmit empty interrupt is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr/fifo becomes empty. 2.6 receiver the receiver section contains an 8-bit receive shift register (rsr) and 16 bytes of fifo which includes a byte-wide receive holding register (rhr). the rsr uses the 16x clock for timing. it verifies and validates every bit on the incoming char acter in the middle of each data bit. on the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16x clock rate. after 8 clocks the start bit period should be at the center of the start bit. at this time the start bit is sa mpled and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false character. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if there were any error(s), they are reported in the lsr register bits 2-4. upon unloading the receive data byte from rhr, the receive fifo pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data re ady interrupt upon receiving a character or delay until it reaches the fifo trigger level. furthermore, data deliv ery to the host is guaranteed by a receive data ready time-out interrupt when data is not rece ived for 4 word lengths as defined by lcr[1:0] plus 12 bits time. this is equivalent to 3.7-4.6 character times. the rhr interrupt is enabled by ier bit-0. 2.6.1 receive holding regi ster (rhr) - read-only the receive holding register is an 8-bit register that holds a receive data byte from the receive shift register. it provides the receive data interface to the host processor. the rhr register is part of the receive fifo of 16 bytes by 11-bits wide, the 3 extra bits are fo r the 3 error tags to be reported in lsr register. when the fifo is enabled by fcr bit-0, the rhr contains th e first data character received by the fifo. after the rhr is read, the next character byte is loaded into the rhr and the errors associated with the current data byte are immediately updated in the lsr bits 2-4. f igure 5. t ransmitter o peration in non -fifo m ode transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x clock
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 12 2.7 special (enhanced feature) mode the 155x supports the standard features of the st 16c550. in addition the 155x supports some enhanced features not available for the st16c550. these features are enabled by ier bit-5 and include a software controllable (soft) reset, power down feature and fifo monitoring bits. 2.7.1 soft reset soft resets are useful when the user desires the capa bility of resetting an exter nally connected device only. mcr bit-2 can be used to initiate a soft reset at the rs t output pin. this does not reset the 155x (only the reset input pin can reset the 155x). soft resets from mcr bit-2 are ?ored? with the reset input pin. therefore both reset types will be seen at the rst output pin. 2.7.2 power down mode the power down feature (controlled by mcr bit-7) provides the user wit h the capability to conserve power when the package is not in actual use without destroying internal register configuration data. this allows quick turnarounds from power down to normal operation. 2.7.3 txrdy and rxrdy bits when ier bit-5 is set to a logic 1, isr bits 4 and 5 represent the compliment (inver sion) of the txrdy status and rxrdy status, respectively. see table 1 . f igure 6. r eceiver o peration in non -fifo m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x clock receive data characters data bit validation error tags in lsr bits 4:2
xr st16c1550/51 rev. 4.2.1 2.97v to 5.5v uart with 16-byte fifo 13 2.8 internal loopback the 155x uart provides an internal loopback capability for system diagnostic purposes . the internal loopback mode is enabled by setting mcr register bit-4 to logi c 1. all regular uart functions operate normally. figure 7 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to re ceive the same data that it was sending. the tx pin is held at logic 1 or mark condition while rts# and dtr# are de-asserted, and cts#, dsr# cd# and ri# inputs are ig nored. caution: the rx input must be held to a logic 1 during loopback test else upon exiting the loopback test the uart may detect and report a false ?break? signal. f igure 7. i nternal l oopback tx rx modem / general purpose control logic internal data bus lines and control signals rts# mcr bit-4=1 vcc vcc transmit shift register (thr/fifo) receive shift register (rhr/fifo) cts# dtr# dsr# ri# cd# op1# op2# rts# cts# dtr# dsr# ri# cd# vcc
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 14 3.0 uart internal registers the 155x has a set of configuration registers selected by address lines a0, a1 and a2. the 16c550 compatible registers can be accessed when lcr[7] = 0 and the baud rate generator divisor registers can be accessed when lcr[7] = 1. the complete register set is shown on table 3 and table 4 . t able 3: st16c155x uart internal registers a2,a1,a0 a ddresses r egister r ead /w rite c omments 0 0 0 rhr - receive holding register thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 dll - div latch low byte read/write lcr[7] = 1 0 0 1 dlm - div latch high byte read/write 0 0 1 ier - interrupt enable register read/write lcr[7] = 0 0 1 0 isr - interrupt status register fcr - fifo control register read-only write-only 0 1 1 lcr - line control register read/write 1 0 0 mcr - modem control register read/write lcr[7] = 0 1 0 1 lsr - line status register reserved read-only write-only 1 1 0 msr - modem status register reserved read-only write-only 1 1 1 spr - scratch pad register read/write
xr st16c1550/51 rev. 4.2.1 2.97v to 5.5v uart with 16-byte fifo 15 . t able 4: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 16c550 compatible registers 0 0 0 rhr rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 0 0 0 0 thr wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier rd/wr 0 0 special mode enable (enable isr bits 5-4, fcr bits 5-4, mcr bits 7, 2) 0 modem status int. enable rx line status int. enable tx empty int. enable rx data int. enable 0 1 0 isr rd fifos enabled fifos enabled 0/ 0/ int source bit-3 int source bit-2 int source bit-1 int source bit-0 rxrdy txrdy 0 1 0 fcr wr rx fifo trigger (msb) rx fifo trigger (lsb) 0/ 0/ dma mode enable tx fifo reset rx fifo reset fifos enable tx fifo trigger (msb) tx fifo trigger (lsb) 0 1 1 lcr rd/wr divisor enable set tx break set parity even parity parity enable stop bits word length bit-1 word length bit-0 1 0 0 mcr rd/wr 0/ 0 0 internal loop - back enable (op2#)/ int output enable (op1#)/ rts# output control dtr# output control lcr[7] = 0 power down mode soft reset 1 0 1 lsr rd rx fifo global error thr & tsr empty thr empty rx break rx framing error rx parity error rx over - run error rx data ready 1 1 0 msr rd cd# input ri# input dsr# input cts# input delta cd# delta ri# delta dsr# delta cts# 1 1 1 spr rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 baud rate generator divisor 0 0 0 dll rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 1 0 0 1 dlm rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 16 4.0 internal register descriptions 4.1 receive holding register (rhr) - read- only see?receiver? on page 11. 4.2 transmit holding register (thr) - write-only see?transmitter? on page 10. 4.3 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are r eported in the interrupt status register (isr). 4.3.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = 1) and receive inte rrupts (ier bit-0 = 1) are enabled, the rhr interrupts (see isr bits 2 and 3) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared wh en the fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is rese t when the fifo is empty. 4.3.2 ier versus receive/transmit fifo polled mode operation when fcr bit-0 equals a logic 1 for fifo enable; rese tting ier bits 0-3 enables the st16c155x in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit-1 indicates an overrun error has occurred and that data in the fifo may not be valid. c. lsr bit 2-4 provides the type of receive data erro rs encountered for the data byte in rhr, if any. d. lsr bit-5 indicates thr is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one character in the rx fifo. ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data character in th e non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. ? logic 0 = disable the receive data ready interrupt (default). ? logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this bit enables the transmit ready interrupt which is issued whenever the thr is empt y in the non-fifo mode or when data in the fifo falls below the progra mmed trigger level in the fifo mode. if the thr is empty when this bit is enabled, an interrupt will be generated. note that this interrupt does not behave in the same manner as the industry standard 16c550. see?interrupt clearing:? on page 17. ? logic 0 = disable transmit ready interrupt (default). ? logic 1 = enable transmit ready interrupt.
xr st16c1550/51 rev. 4.2.1 2.97v to 5.5v uart with 16-byte fifo 17 ier[2]: receive line status interrupt enable if any of the lsr register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in fifo. lsr bit-1 generates an interrupt immediately when the character has been received. lsr bits 2-4 generate an in terrupt when the character with errors is read out of the fifo. ? logic 0 = disable the receiver line status interrupt (default). ? logic 1 = enable the receiver line status interrupt. ier[3]: modem status interrupt enable ? logic 0 = disable the modem status register interrupt (default). ? logic 1 = enable the modem status register interrupt. ier[4]: reserved ier[5]: special mode enable ? logic 0 = disable special mode functions (default). ? logic 1 = enable special mode functions in addition to basic st16c1450 functions. enables isr bits 4-5 (txrdy/rxrdy), mcr bit-2 (soft reset) and mcr bit-7 (power down) functions. ier[7:6]: reserved 4.4 interrupt status register (isr) - read-only the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current hi ghest pending interrupt level to be se rviced, others are queued up to be serviced next. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source table, table 5 , shows the data values (bits 0-3) for the inte rrupt priority levels an d the interrupt sources associated with each of these interrupt levels. 4.4.1 interrupt generation: ? lsr is by any of the lsr bits 1, 2, 3 and 4. ? rxrdy is by rx trigger level. ? rxrdy time-out is by a 4-char plus 12 bits delay timer. ? txrdy is by tx trigger level or tx fifo empty. ? msr is by any of the msr bits 0, 1, 2 and 3. 4.4.2 interrupt clearing: ? lsr interrupt is cleared by a read to the lsr register (b ut flags and tags not cleared until character(s) that generated the interrupt(s) has been emptied or cleared from fifo). ? rxrdy interrupt is cleared by reading data until fifo fa lls below the trigger level. ? rxrdy time-out interrupt is cleared by reading rhr until empty. ? txrdy interrupt is cleared by a read to the isr regist er and disabling the txrdy interrupt (set ier bit-1 = 0), or by loading data into the tx fifo. ? msr interrupt is cleared by a read to the msr register.
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 18 ] isr[0]: interrupt status ? logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. ? logic 1 = no interrupt pending (default condition). isr[3:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority leve ls (see interrupt source table 5 ). isr[4]: txrdy this bit represents the compliment (inversion) of the tx rdy status when ier bit-5 is set to a logic 1. see table 1 . isr[5]: rxrdy this bit represents the compliment (inversion) of the rx rdy status when ier bit-5 is set to a logic 1. see table 1 . isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disa bled. they are set to a logic 1 when the fifos are enabled. 4.5 fifo control register (fcr) - write-only this register is used to enable the fifos, clear the fi fos, set the transmit/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: fcr[0]: tx and rx fifo enable ? logic 0 = disable the transmit and receive fifo (default). ? logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed. fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no receive fifo reset (default). ? logic 1 = reset the receive fifo pointers and fifo le vel counter logic (the rece ive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. t able 5: i nterrupt s ource and p riority l evel p riority l evel isr r egister s tatus b its s ource of interrupt b it -3 b it -2 b it -1 b it -0 1 0 1 1 0 lsr (receiver line status register) 2 1 1 0 0 rxrdy (receive data time-out) 3 0 1 0 0 rxrdy (received data ready) 4 0 0 1 0 txrdy (transmit ready) 5 0 0 0 0 msr (modem status register) - 0 0 0 1 none (default)
xr st16c1550/51 rev. 4.2.1 2.97v to 5.5v uart with 16-byte fifo 19 fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no transmit fifo reset (default). ? logic 1 = reset the transmit fifo pointers and fifo le vel counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[3]: dma mode select controls the behavior of the txrdy# and rxrdy# pins. see dma operation section for details. ? logic 0 = normal operation (default). ? logic 1 = dma mode. fcr[5:4]: transmit fifo trigger select these 2 bits are only active when ier bit-5 is a ?1?. (logic 0 = default, tx trigger level = 1) these 2 bits set the trigger level for the transmit fifo. the uart will issue a transmit interrupt when the number of characters in the fifo falls below the selected trigger level, or when it gets empty in case that the fifo did not get filled over the trigger level on last re-load. table 6 shows the selections. fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1) these 2 bits are used to se t the trigger level for the receive fifo. th e uart will issue a rece ive interrupt when the number of the characters in the fifo crosses the trigger level. table 6 shows the complete selections. 4.6 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. t able 6: t ransmit and r eceive fifo t rigger l evel s election fcr b it -7 fcr b it -6 fcr b it -5 fcr bit -4 r eceive t rigger l evel t ransmit t rigger l evel 0 0 1 1 0 1 0 1 1 4 8 14 0 0 1 1 0 1 0 1 1 4 8 14 bit-1 bit-0 w ord length 0 0 5 (default) 0 1 6 1 0 7 1 1 8
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 20 lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bi t in conjunction with the programmed word length. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the pa rity bit is a simple way used in communications for data integrity check. see table 7 for parity selection summary below. ? logic 0 = no parity. ? logic 1 = a parity bit is generated during the transmissi on while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logi c 1, lcr bit-4 selects the even or odd parity format. ? logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format (default). ? logic 1 = even parity is gen erated by forcing an even numb er of logic 1?s in the tr ansmitted character. the receiver must be programmed to check the same format. lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit- 5 selects the forced parity format. ? lcr[5] = logic 0, parity is not forced (default). ? lcr[5] = logic 1 and lcr[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. ? lcr[5] = logic 1 and lcr[4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. lcr[6]: transmit break enable when enabled, the break control bit causes a break cond ition to be transmitted (the tx output is forced to a ?space?, logic 0, state). this co ndition remains, until disabled by setting lcr bit-6 to a logic 0. ? logic 0 = no tx break condition (default). ? logic 1 = forces the transmitter output (tx) to a ?space ?, logic 0, for alerting the remote receiver of a line break condition. bit-2 w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2 t able 7: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity to mark, ?1? 1 1 1 forced parity to space, ?0?
xr st16c1550/51 rev. 4.2.1 2.97v to 5.5v uart with 16-byte fifo 21 lcr[7]: baud rate divisors enable baud rate generator divisor (dll/dlm) enable. ? logic 0 = data registers are selected (default). ? logic 1 = divisor latch registers are selected. 4.7 modem control register (mcr) or general purpose outputs control - read/write the mcr register is used for controlling the serial/mod em interface signals or g eneral purpose inputs/outputs. mcr[0]: dtr# output the dtr# pin is a modem control outpu t. if the modem interface is not us ed, this output may be used as a general purpose output. ? logic 0 = force dtr# output to a logic 1 (default). ? logic 1 = force dtr# output to a logic 0. mcr[1]: rts# output the rts# pin is a modem control output. if the modem in terface is not used, this output may be used as a general purpose output. ? logic 0 = force rts# output to a logic 1 (default). ? logic 1 = force rts# output to a logic 0. mcr[2]: op1# output/soft reset op1# is not available as an output pin on the 155x. bu t it is available for use during internal loopback mode. in the loopback mode, this bit is used to write the state of the modem ri# interface signal. ? logic 0 = op1# output (ri# inpu t) is at logic 1 (default). ? logic 1 = op1# output (ri# input) is at logic 0. in normal operation, this bit is associated with the rst (b uffered reset) output pin. the logical state of the rst pin will follow exactly the logical state of the reset pin. when ier bit-5 = 1, soft resets fr om mcr bit-2 are ored with the state of the reset input pin. therefore both reset types will be seen at the rst pin. note that asserting mcr bit-2 does not reset the 155x. ? logic 0 = the rst output pin is a logic 0 (default). ? logic 1 = the rst output pin is a logic 1. mcr[3]: op2# or int output enable when not in internal loopback mode: ? logic 0 = int output is three-state (default). ? logic 1 = int output is active high. op2# is not available as an output pin on the 155x. bu t it is available for use during internal loopback mode. in the loopback mode, this bit is used to write the state of the modem cd# interface signal. ? logic 0 = op2# output (cd# input) is a logic 1 (default). ? logic 1 = op2# output (cd# input) is a logic 0. mcr[4]: internal loopback enable ? logic 0 = disable loopback mode (default). ? logic 1 = enable local loopback mode, see loopback section and figure 7 . mcr[6:5]: reserved
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 22 mcr[7]: power down enable this bit can only be accessed when ier bit-5 = 1. ? logic 0 = normal mode (default). ? logic 1 = power down mode. see?power down mode? on page 12. 4.8 line status register (lsr) - read only this register provides the status of data transfers between the uart and the host. if ier bit-2 is set to a logic 1, an lsr interrupt will be generated wh en the character that is ready to be read from the rx fifo has an error (parity, framing, overrun, break). lsr[0]: receive data ready indicator ? logic 0 = no data in receive holding register or fifo (default). ? logic 1 = data has been received and is save d in the receive holding register or fifo. lsr[1]: receiver overrun error flag ? logic 0 = no overrun error (default). ? logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while the fi fo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. lsr[2]: receive data parity error tag ? logic 0 = no parity error (default). ? logic 1 = parity error. the received character in rhr does not have correct parity information and is suspect. this error is associated with the character available fo r reading in rhr. lsr[3]: receive data framing error tag ? logic 0 = no framing error (default). ? logic 1 = framing error. the received character did not ha ve a valid stop bit(s). this error is associated with the character available for reading in rhr. lsr[4]: receive break error tag ? logic 0 = no break condition (default). ? logic 1 = the receiver received a break signal (rx was a logic 0 for at least one character frame time). in the fifo mode, only one break character is loaded into the fifo. the break indication remains until the rx input returns to the idle condition, ?mark? or logic 1. lsr[5]: transmit holding register empty flag this bit is the transmit holding register empty indicator. the thr bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to th e transmit shift register. the bit is reset to logic 0 concurrently with the data loading to the transmit holding r egister by the host. in the fifo mode this bit is set when the transmit fifo is empty, it is cleared when the transmit fifo contains at least 1 byte. lsr[6]: thr and tsr empty flag this bit is set to a logic 1 whenever the transmitter goes idle. it is set to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bi t is set to a logic 1 whenever the transmit fifo and transmit shift register are both empty. lsr[7]: receive fifo data error flag ? logic 0 = no fifo error (default). ? logic 1 = a global indicator for the sum of all error bits in the rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit clears when there is no more error(s) in any of the bytes in the rx fifo.
xr st16c1550/51 rev. 4.2.1 2.97v to 5.5v uart with 16-byte fifo 23 4.9 modem status register (msr) - read only this register provides the current state of the modem interf ace input signals. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem changes state. these bits may be used for general purpose inputs when they are not used with modem signals. msr[0]: delta cts# input flag ? logic 0 = no change on cts# input (default). ? logic 1 = the cts# input has changed state since the la st time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[1]: delta dsr# input flag ? logic 0 = no change on dsr# input (default). ? logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[2]: delta ri# input flag ? logic 0 = no change on ri# input (default). ? logic 1 = the ri# input has changed from a logic 0 to a logic 1, ending of the ringi ng signal. a modem status interrupt will be ge nerated if msr in terrupt is enabled (ier bit-3). msr[3]: delta cd# input flag ? logic 0 = no change on cd# input (default). ? logic 1 = indicates that the cd# input has changed st ate since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3). msr[4]: cts input status cts# (active high, logical 1). normally this bit is the compliment of the cts# input. in the loopback mode, this bit is equivalent to bit-1 in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status dsr# (active high, logical 1). normally this bit is the compliment of the dsr# input. in the loopback mode, this bit is equivalent to bit-0 in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used. msr[6]: ri input status ri# (active high, logical 1). no rmally this bit is the compliment of the ri # input. in the loopback mode this bit is equivalent to bit-2 in the mcr register. the ri# i nput may be used as a general purpose input when the modem interface is not used. msr[7]: cd input status cd# (active high, logical 1). normally this bit is the co mpliment of the cd# input. in the loopback mode this bit is equivalent to bit-3 in the mcr register. the cd# i nput may be used as a general purpose input when the modem interface is not used. 4.10 scratch pad register (spr) - read/write this is a 8-bit general purpose register for the user to store temporary data. the content of this register is preserved during sleep mode but becomes 0xff (default) after a reset or a power off-on cycle.
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 24 t able 8: uart reset conditions registers reset state dll bits 7-0 = 0xxx dlm bits 7-0 = 0xxx rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x00 mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs inverted spr bits 7-0 = 0xff i/o signals reset state tx logic 1 rts# logic 1 dtr# logic 1 rst logic 1 int three-state condition
xr st16c1550/51 rev. 4.2.1 2.97v to 5.5v uart with 16-byte fifo 25 test 1: the following inputs should remain steady at vcc or gnd state to minimize power down current: a0-a2, d0-d7, ior#, iow#, cs# and modem inputs. also, rx input must idle at logic 1 state while in power down mode. absolute maximum ratings power supply range 7 volts voltage at any pin gnd-0.3 v to 7 v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw typical package therma l resistance data ( margin of error : 15%) thermal resistance (48-tqfp) theta-ja = 59 o c/w, theta-jc = 16 o c/w thermal resistance (28-plcc) theta-ja = 55 o c/w, theta-jc = 28 o c/w electrical characteristics dc electrical characteristics u nless otherwise noted : ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.97v to 5.5v s ymbol p arameter l imits 3.3v m in m ax l imits 5.0v m in m ax u nits c onditions v ilck clock input low level -0.3 0.6 -0.5 0.6 v v ihck clock input high level 2.4 vcc 3.0 vcc v v il input low voltage -0.3 0.8 -0.5 0.8 v v ih input high voltage 2.0 vcc 2.2 vcc v v ol output low voltage 0.4 v i ol = 6 ma v ol output low voltage 0.4 v i ol = 4 ma v oh output high voltage 2.4 v i oh = -6 ma v oh output high voltage 2.0 v i oh = -1 ma i il input low leakage current 10 10 ua i ih input high leakage current 10 10 ua c in input pin capacitance 5 5 pf i cc power supply current 1.3 3 ma i pwrdn power down current 50 200 ua see test 1
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 26 ac electrical characteristics ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.97v to 5.5v s ymbol p arameter l imits 3.3v m in m ax l imits 5.0v m in m ax u nit c onditions clk clock pulse duration 63 21 ns osc oscillator/external clock frequency 8 24 mhz t as address setup time 5 0 ns t ah address hold time 10 5 ns t cs chip select width 50 40 ns t rd ior# strobe width 35 25 ns t dy read/write cycle delay 40 30 ns t rdv data access time 35 25 ns t dd data disable time 0 25 0 15 ns t wr iow# strobe width 40 25 ns t ds data setup time 20 15 ns t dh data hold time 5 5 ns t wdo delay from iow# to output 50 40 ns 100 pf load t mod delay to set interrupt from modem input 40 35 ns 100 pf load t rsi delay to reset interrupt from ior# 40 35 ns 100 pf load t ssi delay from stop to set interrupt 1 1 bclk t rri delay from ior# to reset interrupt 45 40 ns 100 pf load t si delay from stop to interrupt 45 40 ns t int delay from initial int re set to transmit start 8 24 8 24 bclk t ssr delay from stop to reset rxrdy 1 1 bclk t rr delay from ior# to set rxrdy 45 40 ns t wt delay from iow# to reset txrdy 45 40 ns t srt delay from center of start to set txrdy 8 8 bclk t rst reset pulse width 40 40 ns n baud rate divisor 1 2 16 -1 1 2 16 -1 - bclk baud clock 16x of data rate hz
xr st16c1550/51 rev. 4.2.1 2.97v to 5.5v uart with 16-byte fifo 27 f igure 8. c lock t iming f igure 9. m odem i nput /o utput t iming osc clk clk external clock iow# iow rts# dtr# cd# cts# dsr# int ior# ior ri# t wdo t mod t mod t rsi t mod active active change of state change of state active active active change of state change of state change of state active active
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 28 f igure 10. d ata b us r ead t iming f igure 11. d ata b us w rite t iming t as t dd t ah t rd t rdv t dy t dd t rdv t ah t as t cs valid address valid address valid data valid data a0- a2 cs2# ior# d0-d7 t cs t rd t as t dh t ah t wr t ds t dy t dh t ds t ah t as t cs valid address valid address valid data valid data a0- a2 cs2# iow# d0-d7 t cs t wr
xr st16c1550/51 rev. 4.2.1 2.97v to 5.5v uart with 16-byte fifo 29 f igure 12. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] f igure 13. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] rx rxrdy (isr bit-5) ior# int d0:d7 start bit d0:d7 stop bit d0:d7 t ssr 1 byte in rhr active data ready active data ready active data ready 1 byte in rhr 1 byte in rhr t ssr t ssr rxnfm t rr t rr t rr t ssr t ssr t ssr (reading data out of rhr) tx txrdy (isr bit-4) iow# int* d0:d7 start bit d0:d7 stop bit d0:d7 t wt txnonfifo t wt t wt t srt t srt t srt *int is cleared when the isr is read and ier[1] is disabled. int cleared* int cleared* int cleared* (loading data into thr) (unloading) ier[1] enabled ier[1] enabled ier[1] enabled
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 30 f igure 14. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] f igure 15. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] rx rxrdy (isr bit-5) ior# int d0:d7 s t ssr rxintdma# rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties first byte is received in rx fifo d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo) rx rxrdy (isr bit-5) ior# int d0:d7 s t ssr rxfifodma rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo)
xr st16c1550/51 rev. 4.2.1 2.97v to 5.5v uart with 16-byte fifo 31 f igure 16. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] f igure 17. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] tx txrdy (isr bit-4) iow# int* txdma# d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit (loading data into fifo) last data byte transmitted tx fifo drops below trigger level data in tx fifo tx fifo empty t wt t srt tx fifo empty t t s t si int cleared* *int is cleared when the isr is read and ier[1] is disabled. tx fifo above trigger level and ier[1] enabled. tx txrdy (isr bit-4) iow# int* d0:d7 s txdma d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t (loading data into fifo) last data byte transmitted tx fifo drops below trigger level at least 1 empty location in fifo t srt tx fifo full t wt t si int cleared* *int cleared when the isr is read and ier[1] is disabled. tx fifo above trigger level and ier[1] enabled.
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 32 package dimensions (48 pin tqfp - 7 x 7 x 1 mm ) note: the control dimensio n is the millimeter column inches millimeters symbol min max min max a 0.039 0.047 1.00 1.20 a1 0.002 0.006 0.05 0.15 a2 0.037 0.041 0.95 1.05 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.346 0.362 8.80 9.20 d1 0.272 0.280 6.90 7.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 0 7 0 7 36 25 24 13 1 1 2 37 48 d d 1 d d 1 b e a 2 a 1 a seating plane l c
xr st16c1550/51 rev. 4.2.1 2.97v to 5.5v uart with 16-byte fifo 33 package dimensions (28 pin plcc) note: the control dimension is the inch column inches millimeters symbol min max min max a 0.165 0.180 4.19 4.57 a1 0.090 0.120 2.29 3.05 a2 0.020 - 0.51 - b 0.013 0.021 0.33 0.53 b1 0.026 0.032 0.66 0.81 c 0.008 0.013 0.19 0.32 d 0.485 0.495 12.32 12.57 d1 0.450 0.456 11.43 11.58 d2 0.390 0.430 9.91 10.92 d3 0.300 typ. 7.62 typ. e 0.050 bsc 1.27 bsc h1 0.042 0.056 1.07 1.42 h2 0.042 0.048 1.07 1.22 r 0.025 0.045 0.64 1.14
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 34 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and schedules contai ned here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2005 exar corporation datasheet august 2005. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. revision history d ate r evision d escription january 2003 rev 4.0.0 changed to standard style format. clarified that the tx interrupt is not ms windows compatible. clarified timing diagrams. r enamed rclk (receive clock) to bclk (baud clock) and timing symbols. added t ah , t cs and osc. april 2003 rev 4.0.1 updated ordering information. september 2003 rev 4.1.0 added status column to ordering information. october 2003 rev 4.2.0 clarified compatibility to industry standard 16550 and ms windows standard serial port driver in general description. removed auto rts flow control from mcr bit-1 description since that feature is not available in this device. august 2005 rev 4.2.1 removed discontinued 28-pin pdip from datasheet.
xr st16c1550/51 rev. 4.2.1 2.97v to 5.5v uart with 16-byte fifo i table of contents general description........ ................. ................ ................ ............... .............. ........... 1 f eatures ............................................................................................................................... ...................... 1 a pplications ............................................................................................................................... ................ 1 f igure 1. b lock d iagram ............................................................................................................................... .............................. 1 f igure 2. st16c1550 p inouts ............................................................................................................................... ...................... 2 f igure 3. st16c1551 p inouts ............................................................................................................................... ...................... 3 ordering information ............................................................................................................................... .4 pin descriptions ............ ................ ................ ................. ................ ................. ........... 5 data bus interface ............................................................................................................. ................................ 5 modem or serial i/o interface .................................................................................................. ..................... 5 ancillary signals .............................................................................................................. .................................. 6 1.0 product description ..................................................................................................... ............... 7 enhanced features .............................................................................................................. ....................................... 7 ............................................................................................................................... ..................................................... 7 data rate ...................................................................................................................... .............................................. 7 2.0 functional descriptions ................................................................................................. ........... 8 2.1 internal registers ...................................................................................................... ............................. 8 2.2 dma mode ................................................................................................................ ...................................... 8 t able 1: txrdy and rxrdy b its in fifo and dma m ode ........................................................................................................ 8 2.3 crystal oscillator or exte rnal clock ............ .............. .............. ........... ........... ........... ........... ..... 8 f igure 4. t ypical oscillator connections ............................................................................................................................... .. 9 2.4 programmable baud rate generat or .......... .............. .............. .............. .............. ........... ........... ..... 9 t able 2: t ypical data rates with a 14.7456 mh z crystal or external clock ...................................................................... 10 2.5 transmitter ............................................................................................................. .................................. 10 2.5.1 transmit holding register (thr) - write only........................................................................... .............. 10 2.5.2 transmitter operation in non-fifo mode ................................................................................. ................. 11 f igure 5. t ransmitter o peration in non -fifo m ode .............................................................................................................. 11 2.5.3 transmitter operation in fifo mode ..................................................................................... ...................... 11 2.6 receiver ................................................................................................................ ...................................... 11 2.6.1 receive holding register (rhr) - read-only ............................................................................. ............... 11 f igure 6. r eceiver o peration in non -fifo m ode .................................................................................................................... 12 2.7 special (enhanced feature) mode ............ .............. .............. .............. .............. ............ ......... .......... 12 2.7.1 soft reset ............................................................................................................. ................................................. 12 2.7.2 power down mode ........................................................................................................ ....................................... 12 2.7.3 txrdy and rxrdy bits ................................................................................................... ...................................... 12 2.8 internal loopback ........... .............. .............. .............. .............. .............. ........... .......... .......................... 13 f igure 7. i nternal l oopback ............................................................................................................................... ...................... 13 3.0 uart internal registers ................................................................................................. .......... 14 t able 3: st16c155x uart internal registers ......................................................................................... ...................... 14 t able 4: internal registers description. s haded bits are enabled when efr b it -4=1......................................... 15 4.0 internal register descriptions .......................................................................................... .. 16 4.1 receive holding register (rhr) - read- only . .............. .............. .............. ........... ........... ............ .. 16 4.2 transmit holding register (thr) - write-only ............................................................................ 16 4.3 interrupt enable register (ier ) - read/write .......... .............. .............. .............. .............. .......... . 16 4.3.1 ier versus receive fifo interrupt mode operation ....................................................................... ...... 16 4.3.2 ier versus receive/transmit fifo polled mode operation................................................................ 16 4.4 interrupt status register (isr) - read-only ............................................................................. .. 17 4.4.1 interrupt generation: .................................................................................................. .................................... 17 4.4.2 interrupt clearing: .................................................................................................... ....................................... 17 t able 5: i nterrupt s ource and p riority l evel ....................................................................................................................... 18 4.5 fifo control register (fcr) - write-only ................................................................................ ..... 18 t able 6: t ransmit and r eceive fifo t rigger l evel s election .............................................................................................. 19 4.6 line control register (lcr) - read/write ................................................................................ ..... 19 t able 7: p arity selection ............................................................................................................................... ........................... 20 4.7 modem control register (mcr) or gene ral purpose outputs control - read/write 21 4.8 line status register (lsr) - read only .................................................................................. ......... 22 4.9 modem status register (msr) - read only ................................................................................. ... 23 4.10 scratch pad register (spr) - read/write ................................................................................ .... 23 t able 8: uart reset conditions..................................................................................................... ................................... 24
st16c1550/51 xr 2.97v to 5.5v uart with 16-byte fifo rev. 4.2.1 ii absolute maximum ratings........... ................ ................ ............... .............. ...........25 t ypical package thermal resistance data ( margin of error : 15%)..................................................25 electrical characteristics ........ ................ ................ ............... .............. ...........25 dc e lectrical c haracteristics ..............................................................................................................25 ac e lectrical c haracteristics ..............................................................................................................26 ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.97v to 5.5v ......................26 f igure 8. c lock t iming ............................................................................................................................... ................................ 27 f igure 9. m odem i nput /o utput t iming ............................................................................................................................... ....... 27 f igure 10. d ata b us r ead t iming ............................................................................................................................... ............... 28 f igure 11. d ata b us w rite t iming ............................................................................................................................... .............. 28 f igure 12. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] ............................................................................................ 29 f igure 13. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] .......................................................................................... 29 f igure 14. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] .......................................................................... 30 f igure 15. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] ........................................................................... 30 f igure 16. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] .............................................................. 31 f igure 17. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ]............................................................... 31 p ackage d imensions (48 pin tqfp - 7 x 7 x 1 mm ) ....................................................................................32 p ackage d imensions (28 pin plcc) .........................................................................................................33 r evision h istory ............................................................................................................................... ........34 t able of c ontents ................ ................. ................ ................ ................. .............. ............i
st16c1551 -uart with 16-byte fifos home news careers investor relations contact us partnernet login search communications interface power management support info request how to order samples how to buy design technical documentation technical faqs product finder product tree technical support packaging evaluation boards cross references product change notifications obsolescence interface brochure ibis models bsdl ici uart finder st16c1551 print this page uart with 16-byte fifos features l pin and functionally compatible to ssi 73m1550/2550 software compatible to ins8250, ns16c550 l 1.5 mbps transmit/receive operation (24mhz max.) with programmable clock control l 16 byte transmit fifo l 16 byte receive fifo with error flags l four independently selectable transmit and receive fifo interrupt trigger levels l modem control signals (-cts, -rts, -dsr, -dtr, -ri, -cd) l programmable character lengths (5, 6, 7, 8) with even, odd, or no parity l crystal or external clock input (except 28 pin st16c1551) l provides enhanced 16c550 features for power down and software controllable reset output l 460.8 kbps transmit/receive operation with 7.3728 mhz crystal or external clock source l pb-free, rohs compliant versions offered applications l battery operated electronics l internet appliances l handheld terminal l personal digital assistants l cellular phones dataport description the st16c1550, st16c1551 series (here on denoted as the 155x) is a universal asynchronous receiver and transmitter (uart). the 155x is an improved version of the ssi 73m1550 and ssi 73m2550 uart with higher operating speed and lower access time. the 155x provides enhanced uart functions with 16 byte fifos, a modem control interface, independent programmable baud rate generators with clock rates to 1.5 mbps. onboard status registers provide the user with error indications and operational status. system interrupts and modem control features may be tailored by external software to meet specific user requirements. an internal loopback capability allows onboard diagnostics. the 155x is available in a 28-pin plcc/plastic-dip, 48-pin tqfp packages. specifications ch 1 cpuinterface intel data rate@5/3.3/2.5v 1.5/0.5/na tx/rxfifo(bytes) 16/16 tx/rxfifoctrs no tx/rxfifoint trig 4 levels/ 4 levels autorts/cts no irdasup no 5vtolinputs no sup v 2.97-5.5 pkgs plcc-28, tqfp-48 documents datasheets datasheet version 4.2.1 august 2005 741.38 kb application notes dan-107, interfacing 16cxxx uarts to a cpu version 1.0.0 august 1999 32.43 kb dan-108, uart crystal oscillator design guide version 1.0.0 march 2000 58.16 kb http://www.exar.com/common/content/productdetails.aspx?id=st16c1551 (1 of 2) [26-aug-09 10:59:41 am]
st16c1551 -uart with 16-byte fifos quality and reliability quality & reliability homepage material declaration sheets quality manual quarterly quality & reliability report rohs-green solutions the baud rate generator can be configured for either crystal or external clock input with the exception of the 28 pin 1551 package. an external clock must be provided for the 28 pin 1551 package. each package type, with the exception of the 28 pin 1550, provides a buffered reset output that can be controlled through user software. dma monitor signals txrdy/rxrdy are not available at the 155x i/o pins but these signals are accessible through isr register bits 4-5. except as listed above, each package version has the same features. the 155x is functionally compatible with the 16c550. the 155x is fabricated in an advanced cmos process to achieve low drain power and high speed requirements. for uart technical support or to obtain an ibis model for this product, please email exar's uart technical support group. part number pkg code rohs min temp. (c) max temp. (c) status buy now order samples ST16C1551CJ28-F plcc28 0 70 active st16c1551cq48-f tqfp48 0 70 active st16c1551ij28-f plcc28 -40 85 active st16c1551iq48-f tqfp48 -40 85 active part status legend active - the part is released for sale, standard product. eol (end of life) - the part is no longer being manufactured, there may or may not be inventory still in stock. cf (contact factory) - the part is still active but customers should check with the factory for availability. longer lead-times may apply. pre (pre-introduction) - the part has not been introduced or the part number is an early version available for sample only. obs (obsolete) - the part is no longer being manufactured and may not be ordered. nrnd (not recommended for new designs) - the part is not recommended for new designs. an-1450/an-1550, st16c1450 and st16c1550 application example version 1.0.0 december 1996 43.29 kb general uart application note version 1.0.0 december 1996 39.81 kb ? 2000-2009 exar corporation, fremont california, u.s.a. terms of use | site map http://www.exar.com/common/content/productdetails.aspx?id=st16c1551 (2 of 2) [26-aug-09 10:59:41 am]

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